Verilog Styles for Synthesis of Digital Systems by David R. Smith and Paul D....
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Verilog Styles for Synthesis of Digital Systems by David R. Smith and Paul D....
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eBay-Artikelnr.:136149702135
Artikelmerkmale
- Artikelzustand
- ISBN
- 9780201618600
Über dieses Produkt
Product Identifiers
Publisher
Prentice Hall PTR
ISBN-10
0201618605
ISBN-13
9780201618600
eBay Product ID (ePID)
664632
Product Key Features
Number of Pages
336 Pages
Language
English
Publication Name
Verilog Styles for Synthesis of Digital Systems
Subject
Computer Engineering, Logic Design
Publication Year
2019
Type
Textbook
Subject Area
Computers
Format
Trade Paperback
Dimensions
Item Height
0.7 in
Item Weight
16.8 Oz
Item Length
9.1 in
Item Width
6.9 in
Additional Product Features
Intended Audience
College Audience
LCCN
00-025783
Dewey Edition
21
Illustrated
Yes
Dewey Decimal
621.39/2
Table Of Content
(NOTE: Most chapters begin with Introduction and end with Conclusion, Exercises, and References.) 1. Introduction. References. 2. Basic Language Constructs. Preliminaries. Datatypes. Modules. 3. Structural and Behavioral Specification. Basic Gates. Modeling Levels. Writing Styles. Synthesizable Operations. Continuous Assignments. 4. Simulation. Types of Simulators. Using the VCS Simulator. Testbenches. Debugging. 5. Procedural Specification. The Always Block. Functions and Tasks. Blocking and Non-Blocking Assignments. Control Constructs. Synthesis of Conditional Constructs. Example: Combinational Modules. Flipflops versus Latches. Memory. 6. Design Approaches for Single Modules. Basic Design Methodology. The Specification. Structuring the Design. Design Example 1--A Simple Down Counter. Example 2--Unsigned Parallel-Serial Multiplier. An Alternative Approach to Specifying Flipflops. Common Problems and Fixes. Debugging Strategies. 7. Validation of Single Modules. Sources of Verification Vectors. Verification Testbench Coding Approaches. Post-Synthesis Verification. Formal Verification. System-Level Verification. 8. Finite State Machine Styles. Synthesis of State Machines. Example Specifications. 9. Control-Point Writing Style. Instantiation of Parameterized Modules. Control-Point Style. Using Vendor's Components. 10. Managing Complexity--Large Designs. Steps in High-Level Design. Design Partitioning. Controller Design Styles. Example of Explicit Style--Motion Estimator. Example of Implicit Style--Cache Store. Another Implicit Style Example: MIPS200. 11. Improving Timing, Area, and Power. Timing Issues in Design. Low Power Design. Area Issues in Design. 12. Design Compilation. Running Example: Alarm Clock. Setting Up. Invoking Synthesis. The Log File. 13. Synthesis to Standard Cells. Synthesis Flow. 14. Synthesis to FPGA. FPGA as a Target Technology. Using the Altera Tools. Using the Xilinx Tools. Generating Memory Arrays. Using Embedded Arrays as ROM. FPGA Reports. Gate-Level Simulation. 15. Gate Level Simulation and Testing. Ad-Hoc Test Techniques. Scan Insertion in Synthesis. Built-in Self-Test. 16. Alternative Writing Styles. Behavioral Compiler Styles. Self-Timed Style. Encapsulated Style. Future HDL Development. 17. Mixed Technology Design. Digital/Analog. Hardware/Software. A Small Example. Appendix A: Verilog Examples. Combinational Logic Structures. Sequential Logic Structures. Appendix B: http://www.prenhall.com/smith/franzon. Index.
Synopsis
This book is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to those just entering the field. The text uses a simpler language (Verilog) and standardizes the methodology to the point where even novices can get medium complex designs through to gate-level simulation in a short period of time. Requires a working knowledge of computer organization, Unix, and X windows. Some knowledge of a programming language such as C or Java is desirable, but not necessary. Features a large number of worked examples and problems--from 100 to 100k gate equivalents--all synthesized and successfully verified by simulation at gate level using the VCS compiled simulator, the FPGA Compiler and Behavioral Compiler available from Synopsys, and the FPGA tool suites from Altera and Xilinx. Basic Language Constructs. Structural and Behavioral Specification. Simulation. Procedural Specification. Design Approaches for Single Modules. Validation of Single Modules. Finite State Machine Styles. Control-Point Writing Style. Managing Complexity--Large Designs. Improving Timing, Area, and Power. Design Compiler. Synthesis to Standard Cells. Synthesis to FPGA. Gate Level Simulation and Testing. Alternative Writing Styles. Mixed Technology Design. For anyone wanting an accessible, accelerated introduction to the cutting-edge tools for Digital Hardware Design., For senior/graduate-level courses in Digital Hardware Design/Verilog. This text is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to students e.g., synthesis from high-level specifications, and field programmable gate arrays (FPGA) for many applications. The text uses a simpler language (Verilog) and standardizes the methodology to the point where seniors and first-year graduates can get medium complex designs through to gate-level simulation in a single semester.
LC Classification Number
TK7895.G36S65 2001
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