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eBay-Artikelnr.:333724569844
Artikelmerkmale
- Artikelzustand
- PublishedOn
- 2007-12-12
- Title
- Verification Techniques for System-Level Design (Systems on Sili
- Artist
- Not Specified
- ISBN
- 9780123706164
Über dieses Produkt
Product Identifiers
Publisher
Elsevier Science & Technology
ISBN-10
0123706165
ISBN-13
9780123706164
eBay Product ID (ePID)
61076749
Product Key Features
Number of Pages
256 Pages
Language
English
Publication Name
Verification Techniques for System-Level Design
Subject
Systems Architecture / General, Industrial Design / Product, Electronics / Microelectronics, Software Development & Engineering / Systems Analysis & Design
Publication Year
2007
Type
Textbook
Subject Area
Computers, Technology & Engineering
Series
Systems on Silicon Ser.
Format
Hardcover
Dimensions
Item Height
0.3 in
Item Weight
23.6 Oz
Item Length
9.3 in
Item Width
7.5 in
Additional Product Features
Intended Audience
Scholarly & Professional
LCCN
2007-028038
Dewey Edition
22
Illustrated
Yes
Dewey Decimal
621.3815
Synopsis
This book will explain how to verify SoC logic designs using ?formal? and ?semi-formal? verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in ?functional? verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. ? First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. ? Formal verification of high-level designs (RTL or higher). ? Verification techniques are discussed with associated system-level design methodology., This book will explain how to verify SoC (Systems on Chip) logic designs using "formal" and "semiformal" verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional" verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs., This book will explain how to verify SoC (Systems on Chip) logic designs using "formal" and "semiformal" verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional" verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity. For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs., This book will explain how to verify SoC (Systems on Chip) logic designs using "formal" and "semiformal" verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional" verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity. For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs. - First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs. - Formal verification of high-level designs (RTL or higher). - Verification techniques are discussed with associated system-level design methodology.
LC Classification Number
TK7895.E42F95 2007
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Verkäuferbewertungen (546'365)
- e***f (2360)- Bewertung vom Käufer.Letzter MonatBestätigter KaufEXCELLENT SERVICE THANK YOU
- .***c (4884)- Bewertung vom Käufer.Letzter MonatBestätigter KaufOne of eBay’s finest!! Thanks for a swift and smooth transaction!! AAAAA *****
- r***e (439)- Bewertung vom Käufer.Letzter MonatBestätigter KaufGoodah