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Artikelmerkmale
- Artikelzustand
- ISBN-13
- 9783540786092
- Book Title
- Reconfigurable Computing: Architectures, Tools, and Applications
- ISBN
- 9783540786092
Über dieses Produkt
Product Identifiers
Publisher
Springer Berlin / Heidelberg
ISBN-10
3540786090
ISBN-13
9783540786092
eBay Product ID (ePID)
65665462
Product Key Features
Number of Pages
Xiv, 346 Pages
Language
English
Publication Name
Reconfigurable Computing - Architectures, Tools, and Applications : 4th International Workshop, ARC 2008, London, UK, March 2008 - Proceedings
Subject
Systems Architecture / General, Hardware / General, Computer Science, General, Logic Design
Publication Year
2008
Type
Textbook
Subject Area
Computers
Series
Lecture Notes in Computer Science Ser.
Format
Trade Paperback
Dimensions
Item Weight
19.4 Oz
Item Length
9.3 in
Item Width
6.1 in
Additional Product Features
Intended Audience
Scholarly & Professional
LCCN
2008-923932
Dewey Edition
22
Series Volume Number
4943
Number of Volumes
1 vol.
Illustrated
Yes
Dewey Decimal
621.39/5
Table Of Content
Keynotes.- Synthesizing FPGA Circuits from Parallel Programs.- From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing.- The von Neumann Syndrome and the CS Education Dilemma.- Programming and Compilation.- Optimal Unroll Factor for Reconfigurable Architectures.- Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems.- DNA and String Processing Applications.- DNA Physical Mapping on a Reconfigurable Platform.- Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension.- Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs.- Scientific Applications.- A Custom Processor for a TDMA Solver in a CFD Application.- A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation.- Reconfigurable Computing Hardware and Systems.- Physical Design of FPGA Interconnect to Prevent Information Leakage.- Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs.- Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems.- Image Processing.- FPGA-Based Real-Time Super-Resolution on an Adaptive Image Sensor.- A Parallel Hardware Architecture for Image Feature Detection.- Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System.- Run-Time Behavior.- A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems.- A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor.- Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens.- Instruction Set Extension.- ARISE Machines: Extending Processors with Hybrid Accelerators.- The Instruction-Set Extension Problem: A Survey.- Random Number Generation and Financial Computation.- An FPGA Run-Time Parameterisable Log-Normal Random Number Generator.- Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA.- Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models.- Posters.- Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.- Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard.- Creating the World's Largest Reconfigurable Supercomputing System Based on the Scalable SGI® Altix® 4700 System Infrastructure and Benchmarking Life-Science Applications.- Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs.- A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures.- PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications.- Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip.- Efficiency of Dynamic Reconfigurable Datapath Extensions - A Case Study.- Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices.- Data Reallocation by Exploiting FPGA Configuration Mechanisms.- A Networked, Lightweight and Partially Reconfigurable Platform.- Neuromolecularware - A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis.- An FPGA Configuration Scheme for Bitstream Protection.- Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture.
Synopsis
For manyyears,the idea of recon'gurablehardwaresystems hasrepresentedthe Holy Grail for computer systemdesigners.It has been recognizedfor a long time that the microprocessor provides high ?exibility but at a very low performance merit in terms of MIPS/W or other such measures. Recon'gurable systems are thus attractive as they can be con'gured to provide the best match for the computational requirements at that speci'c time, giving much better area - speed - power performance. However, the practicalities of achieving such a recon'gurable system are - merous andrequirethe developmentof: suitable recon'gurablehardwareto s- portthe dynamicbehavior;programmingtoolsto allowthe dynamicbehavior of the recon'gurability to be modelled; programming languages to support rec- ?guration;andveri'cationtechniquesthatcandemonstratethatrecon'guration hashappenedcorrectlyateachstage.Whiletheproblemsaremany,theexistence and development of technologies such as the multi-core processor architecture, recon'gurable computing architectures, and application-speci'c processors s- gest there is a strong desire for recon'gurable systems. Moreover, FPGAs also provide the ideal platforms for the development of such platforms. The major motivation behind the International Workshop on Applied - con'gurable Computing (ARC) series is to create a forum for presenting and discussing on-going research e'orts in applied recon'gurable computing. The workshop also focuses on compiler and mapping techniques, and new recon- urablecomputingarchitectures.Theseriesofeditionsstartedin2005inAlgarve, Portugal, followed by the 2006 workshop in Delft, The Netherlands, and last year's workshop in Mangaratiba, Rio de Janeiro, Brazil. As in previous years, selectedpapershavebeenpublished asa SpringerLNCS(LectureNotes in C- puter Science) volume., For manyyears, the idea of recon'gurablehardwaresystems hasrepresentedthe Holy Grail for computer systemdesigners.It has been recognizedfor a long time that the microprocessor provides high ?exibility but at a very low performance merit in terms of MIPS/W or other such measures. Recon'gurable systems are thus attractive as they can be con'gured to provide the best match for the computational requirements at that speci'c time, giving much better area - speed - power performance. However, the practicalities of achieving such a recon'gurable system are - merous andrequirethe developmentof: suitable recon'gurablehardwareto s- portthe dynamicbehavior;programmingtoolsto allowthe dynamicbehavior of the recon'gurability to be modelled; programming languages to support rec- ?guration;andveri'cationtechniquesthatcandemonstratethatrecon'guration hashappenedcorrectlyateachstage.Whiletheproblemsaremany, theexistence and development of technologies such as the multi-core processor architecture, recon'gurable computing architectures, and application-speci'c processors s- gest there is a strong desire for recon'gurable systems. Moreover, FPGAs also provide the ideal platforms for the development of such platforms. The major motivation behind the International Workshop on Applied - con'gurable Computing (ARC) series is to create a forum for presenting and discussing on-going research e'orts in applied recon'gurable computing. The workshop also focuses on compiler and mapping techniques, and new recon- urablecomputingarchitectures.Theseriesofeditionsstartedin2005inAlgarve, Portugal, followed by the 2006 workshop in Delft, The Netherlands, and last year's workshop in Mangaratiba, Rio de Janeiro, Brazil. As in previous years, selectedpapershavebeenpublished asa SpringerLNCS(LectureNotes in C- puter Science) volume., Coverage in this proceedings volume includes DNA and string processing applications, reconfigurable computing hardware and systems, image processing, run-time behavior, instruction set extension, as well as random number generation and financial computation.
LC Classification Number
QA75.5-76.95
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